The NAND flash technology that Toshiba introduced in 1989, making thumb drives, SSDs and your smartphone's memory possible, has finally reached a development dead end.
Toshiba and other major manufacturers of planar floating gate NAND flash are setting those engineering efforts aside and focusing development on 3D NAND, also known as vertical charge trap or floating gate flash and other 3D memories.
Scott Nelson, vice president in charge of Toshiba's memory business, said planar or 2D NAND flash will continue to be sold because there are still many "lower density" applications for it. But the economics of shrinking it below 15nm don't make sense.
"It's just so challenged to shrink it any further. These are baby steps now," Nelson said. "As of now, there's nothing on the roadmap that would indicate another floating gate generation."
Surprisingly, 2D NAND's development demise is a relatively recent, if not unexpected, event. Jim Handy, principal analyst with semiconductor research firm Objective Analysis, about a year ago said he spoke with An Steegen, the vice president of semiconductor research and development at Imec, "and there was a clear path to 13nm for planar NAND." (Imec is the research consortium for semiconductor companies.)
At Semicon, last month, Steegen changed her tune.
"She said that the NAND makers have dropped that project...and were putting all of their resources into 3D," Handy said. "So, yes, planar ends at 15nm."
Toshiba development partner SanDisk said the same in and interview with Computerworld.
In 2013, Samsung became the first to introduce a vertical TLC "V-NAND", a 32-layer cell structure based on Charge Trap Flash (CTF) technology and vertical interconnect process technology to link the cell array. By applying the latter technologies, Samsung's 3D V-NAND can provide over twice the scaling compared to its 20nm-class planar NAND flash.
Samsung's 3D V-NAND chip also provided two to 10 times higher reliability and twice the write performance of its previous planar NAND flash.
Scott DeBoer, vice president of research and development at Micron -- a partner in NAND flash development with Intel -- said their companies' efforts going forward also will also be focused on two new 3D memory technologies.
Intel and Micron are developing a 32-layer 3D NAND flash flash based on a floating gate memory cell; they also recently announced a resistive RAM (ReRAM) memory called 3D XPoint. The 128Gbit chip, based on the new 3D XPoint technology, increases performance and resilience by up to 1,000 times over planar NAND. Intel and Micron said their 3D NAND will hold 256Gbits (32GB) or 384Gbits (48GB) per chip depending on whether it is produced in two-bit per cell or three bit per cell technology.
Micron's and Intel's 32-layer 3D NAND will focus on cutting costs and increasing capacities, while their new 3D XPoint RAM will replace some DRAM and NAND flash for high-performance applications, such as big data analytics.
Intel and Micron heralded 3D XPoint RAM as "the first new class of memory since 1989," referring to floating gate NAND.
3D XPoint, a type of resistive memory that doesn't store an electrical charge, will sport 1,000 times the performance and endurance of planar NAND flash. As far as endurance, it can handle about one million erase-write cycles, meaning the new memory would last pretty much forever. Today's planar NAND sports 3,000 to 10,000 erase-write cycles.
So dense is the XPoint RAM, that for data centers, Intel will be able to fit 1TB on a card just two millimeters thick.
3D XPoint technology is a new class of non-volatile memory that relies on resistance change of the bulk material to achieve non-volatility. Unlike Phase Change Memory, 3D XPoint technology uses a cross-point (XPoint) architecture -- like a 3D lattice -- enabling it to scale in ways that Phase Change Memory can't, Intel said. Unlike Memristors -- another type of resistive memory -- 3D XPoint technology uses the bulk material to switch resistance state and does not rely on statistically variable filaments, enabling it to reach manufacturing.
The combination of architecture and the unique materials in both the memory cell and a selector that enables reads and writes enable 3D XPoint technology to achieve higher density and better performance and endurance.
So why not replace 3D NAND with 3D XPoint memory? It's too expensive to produce, Intel has said. Bcause of its price point, 3D XPoint memory will reside between DRAM, which is faster but more expensive, and 3D NAND, which is cheaper but slower.
With all these new non-volatile memories popping up, planar NAND cannot compete on scale. But, it has had quite a run from the days when it was 130nm in size (in 1989), or even 40nm (in 2006).
Consider this. A strand of human DNA is 2.5 nanometers in diameter, and there are 25,400,000 nanometers in one inch. Now consider that major NAND flash memory makers are mass producing NAND using 15nm and 16nm-sized lithography. That just doesn't leave much room left to further shrink it.
So at the same time manufacturers been shrinking planar NAND process technologies, they've been increasing the number of bits of data the memory can store per transistor or cell. They've moved from one bit in single-level cell (SLC) NAND, to two bits in multi-level cell (MLC) NAND, to three bits in triple-level cell (TLC) NAND.
The problem is that as transistors shrink and bits increase, the electrons that represent the data stored in them leak from one cell to another and create data errors. That means more sophisticated error correction code (ECC) has been needed to keep memory reliable. That, too, has grown increasingly difficult.
The result: Instead of continuing to make memory smaller and denser, manufacturers have begun making vertical NAND like tiny skyscapers -- stacking layers of microscopic NAND atop one another using charge trap technology.
Don't get too nostalgic for planar NAND flash.
Consider Toshiba's and SanDisk's latest 3D NAND chips, which doubled capacity from 128Gbit in a chip announced earlier this year, to 256Gbit in the chip announced this week.
Today, SanDisk offers a 200GB microSD card that's about the size of a thumbnail. Its new 256Gbit chips have to potential to double that capacity to 400GB next year, according to Siva Sivaram, executive vice president of SanDisk's Memory Technology.
"3D NAND effectively gives you back predictability of scaling for quite some time into the future," Sivaram said, referring to the consistent scaling that planar NAND afforded the industry for decades. Planar NAND doubled in capacity every year or so.
SanDisk and Toshiba this week introduced their 48-layer 3D NAND. But 3D NAND technology is expected to reach 100 levels of stacked cells by 2017, according to industry experts. That will allow 1Tbit-per-chip density.
A 1Tbit chip, extrapolated into an SD card's capacity, would mean a product capable of storing 800GB to 1TB of capacity in an object half the size of a postage stamp.
Toshiba and SanDisk are so certain about the future of their 3D NAND that they demolished their Fabrication number 2 plant in Mie prefecture, Japan, and are building a larger wafer fabrication facility on the same site to exclusively produce 3D NAND flash chips. The plant will be completed next year, and products will begin mass production by the second quarter, according to Sivaram.
"Our focus right now is on 3D NAND," Sivaram said. "We're not making another 2D product."
This story, "Today's NAND flash has hit a development dead-end" was originally published by Computerworld.